1. Field of the Invention
The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a three-electrode surface-discharge plasma display panel.
2. Description of the Related Art
FIG. 1 shows a structure of a general three-electrode surface-discharge plasma display panel, FIG. 2 shows an electrode line pattern of the panel shown in FIG. 1, and FIG. 3 shows an example of a pixel of the panel shown in FIG. 1. Referring to the drawings, address electrode lines A1, A2, . . . Am, dielectric layers 11 and 15, Y electrode lines Y1, Y2, . . . Yn, X electrode lines X1, X2, . . . Xn, phosphors 16, partition walls 17 and a MgO protective film 12 are provided between front and rear glass substrates 10 and 13 of a general surface-discharge plasma display panel 1.
The address electrode lines A1, A2, . . . Am are provided on the front surface of the rear glass substrate 13 in a predetermined pattern. The lower dielectric layer 15 covers the entire front surface of the address electrode lines A1, A2, . . . Am. The partition walls 17 are located on the front surface of the lower dielectric layer 15 parallel to the address electrode lines A1, A2, . . . Am. The partition walls 17 define discharge areas of the respective pixels and prevent optical crosstalk among pixels. The phosphors coatings 16 are located between partition walls 17.
The X electrode lines X1, X2, . . . Xn and the Y electrode lines Y1, Y2, . . . Yn are arranged on the rear surface of the front glass substrate 10 orthogonal to the address electrode lines A1, A2, . . . Am, in a predetermined pattern. The respective intersections define corresponding pixels. The X electrode lines X1, X2, . . . Xn and the Y electrode lines Y1, Y2, . . . Yn are each comprised of transparent, conductive indium tin oxide (ITO) electrode lines (Xna and Yna of FIG. 3) and metal bus electrode lines (Xnb and Ynb of FIG. 3). The upper dielectric layer 11 entirely coats the rear surface of the X electrode lines X1, X2, . . . Xn and the Y electrode lines Y1, Y2, . . . Yn. The MgO protective film 12 for protecting the panel 1 against strong electrical fields entirely coats the rear surface of the upper dielectric layer 11. A gas for forming plasma is hermetically sealed in a discharge space 14.
The above-described plasma display panel is basically driven such that a reset step, an address step and a sustain-discharge step are sequentially performed in a unit subfield. In the reset step, wall charges remaining from the previous subfield are erased and space charges are evenly formed. In the address step, the wall charges are formed in a selected pixel area. Also, in the discharge display step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the X electrode lines X1, X2, . . . Xn and the Y electrode lines Y1, Y2, . . . Yn a surface discharge occurs at the pixels at which the wall charges are formed. Here, a plasma is formed in the gas in the discharge space 14 and phosphors 16 are excited by ultraviolet rays and emit light.
FIG. 4 shows the structure of a unit display period based on a driving method of a conventional plasma display panel. Here, a unit display period represents a frame in the case of a progressive scanning method, and a field in the case of an interlaced scanning method. The driving method shown in FIG. 4 is generally referred to as a multiple address overlapping display driving method. According to this driving method, pulses for a display discharge are consistently applied to all X electrode lines (X1, X2, . . . Xn of FIG. 1) and all Y electrode lines (Y1, Y2, . . . Y480) and pulses for resetting or addressing are applied between the respective pulses for a display discharge. In other words, the reset and address steps are sequentially performed with respect to individual Y electrode lines or groups, within a unit sub-field, and then the display discharge step is performed for the remaining time period. Thus, compared to an address-display separation driving method, the multiple address overlapping display driving method has an enhanced displayed luminance. Here, the address-display separation driving method refers to a method in which, within a unit subfield, reset and address steps are performed for all Y electrode lines Y1, Y2, . . . Y480, during a certain period and a display discharge step is then performed.
Referring to FIG. 4, a unit frame is divided into 8 subfields SF1, SF2, . . . SF8 for achieving a time-division gray scale display. In each subfield, reset, address and display discharge steps are performed, and the time allocated to each subfield is determined by a display discharge time. For example, in the case of displaying a 256 step scale with 8-bit video data in the unit of frames, if a unit frame (generally 1/60 seconds) is comprised of 256 unit times, the first subfield SF1, driven by the least significant bit (LSB) video data, has 1 (2xc2x0) unit time, the second subfield SF22 (21) unit times, the third subfield SF34 (22) unit times, the fourth subfield SF48 (23) unit times, the fifth subfield SF516 (24) unit times, the sixth subfield SF632 (25) unit times, the seventh subfield SF764 (26) unit times, and the eighth subfield SF8, driven by the most significant bit (MSB) video data, 128 (26) unit times. In other words, since the sum of unit times allocated to the respective subfields is 257 unit times, 255 steps can be displayed, 256 steps including one step which is not display-discharged at any subfield.
After the address step is performed and the display discharge step is then performed with respect to the first Y electrode line Y1 or the first Y electrode line group, e.g., Y1, Y2, Y3 and Y4, in the first subfield SF1, the address step is performed with respect to the first Y electrode line Y1 or the first Y electrode line group, e.g., Y1, Y2, Y3 and Y4, in the second subfield SF2. This procedure is applied to the subsequent subfields SF3, SF4, . . . SF8 in the same manner. For example, the address step is performed and the display discharge step is then performed with respect to the second Y electrode line Y2 or the second Y electrode line group, e.g. Y5, Y6, Y7 and Y8, in the seventh subfield SF7. Then, in the eighth subfield SF8, the address electrode is performed and the display discharge step is then performed with respect to the second Y electrode step line Y2 or the second Y electrode line group, e.g., Y5, Y6, Y7 and Y8. The time for a unit subfield equals the time for a unit frame. The respective subfields overlap on the basis of the driven Y electrode lines Y1, Y2, . . . Y480, to form a unit frame. Thus, since all subfields SF1, SF2, . . . SF8 exist in every timing, time slots for addressing depending on the number of subfields are set between pulses for display discharging, for the purpose of performing the respective address steps.
As one of the address-display overlapping driving methods, a driving method in which the address step is performed between the pulses for display discharging in the order of subfields SF1, SF2, . . . SF8, is generally used. According to this driving method, after the pulses for display discharges simultaneously applied to the Y electrode lines Y1, Y2, . . . Y480 terminate, the pulses for display discharges simultaneously applied to the X electrode lines X1, X2, . . . Xn start. Also, the scan pulses and the corresponding display data signals are applied after the pulses for display discharges simultaneously applied to the X electrode lines X1, X2, . . . Xnterminate and before the pulses for display discharges simultaneously applied to the Y electrode lines Y1, Y2, . . . Y480 start. Thus, since the pulses for display discharges simultaneously applied to the X electrode lines X1, X2, . . . Xn start at the termination of the pulses for display discharges simultaneously applied to the Y electrode lines Y1, Y2, . . . Y480, subsequent reset or addressing times can be maximally secured, thereby enhancing the resetting or addressing performance.
As described above, there is a relatively large difference between the switching time from the display discharges of the Y electrode lines Y1, Y2, . . . Y480 to the display discharges of the X electrode lines X1, X2, . . . Xn and the switching time from the display discharges of the X electrode lines X1, X2, . . . Xn to the display discharges of the Y electrode lines Y1, Y2, . . . Y480. However, conventionally, the power levels of the pulses for display discharges have been all the same. Thus, according to the conventional driving method, the display discharges of the Y electrode lines Y1, Y2, . . . Y480 have a relatively weak influence on the display discharges of the X electrode lines X1, X2, . . . Xn. On the contrary, the display discharges of the X electrode lines X1, X2, . . . Xn have a relatively stronger influence on the display discharges of the Y electrode lines Y1, Y2, . . . Y480. The non-uniformity in the display discharges deteriorates the performance and efficiency of a display discharge and damages the MgO layer (12 of FIG. 1) as the protective layer, thereby shortening the lifetime of the plasma display panel (1 of FIG. 1).
To solve the above problem, it is an object of the present invention to provide a method for driving a plasma display panel which enhances the performance and efficiency of a display discharge and increase the lifetime of the driven plasma display panel.
To achieve the above object, there is provided a method for driving a plasma display panel having front and rear substrates opposed to and facing each other, X and Y electrode lines formed between the front and rear substrates to be parallel to each other and address electrode lines formed to be orthogonal to the X and Y electrode lines, to define corresponding pixels at interconnections, such that a scan pulse is applied to the respective Y electrode lines with a predetermined time difference and the corresponding display data signals are simultaneously applied to the respective address electrode lines to form wall charges at pixels to be displayed, pulses for a display discharge are alternately applied to the X and Y electrode lines to cause a display discharge at the pixels where the wall charges have been formed, the pulses for display discharges simultaneously applied to the X electrode lines start to occur after the pulses for display discharges simultaneously applied to the Y electrode lines terminate, and the scan pulses and the corresponding display data signals are applied after the pulses for display discharges simultaneously applied to the X electrode lines terminate and before the pulses for display discharges simultaneously applied to the Y electrode lines start to occur, the driving method wherein the power levels of pulses for display discharges simultaneously applied to the Y electrode lines is greater than the power levels of pulses for display discharges simultaneously applied to the X electrode lines.
Accordingly, a difference between the power levels of the pulses for display discharges can compensate for a difference between the switching time from the display discharges of the Y electrode lines to the display discharges of the X electrode lines and the switching time from the display discharges of the X electrode lines to the display discharges of the Y electrode lines. In other words, the non-uniformity in the display discharges can be prevented by relatively strengthening the effects of the display discharges of the X electrode lines on the display discharges of the Y electrode lines, thereby enhancing the performance and efficiency of a display discharge and increasing the lifetime of the driven plasma display panel.